Intel Corp. will reveal details about its third-generation Itanium server processor, which will offer a 1.5GHz clock speed, at a conference sponsored by the Institute of Electrical and Electronics Engineers Inc. (IEEE).
The new Itanium, code-named Madison, is expected to be released in the middle of 2003. Limited specifications of the forthcoming chip are available at the Web site for the International Solid-State Circuits Conference to be held in San Francisco in February.
Current Itanium 2 processors run at 900MHz and 1.0GHz, and come with up to 3MB of Level 3 on-die cache. Madison will double the amount of L3 on-die cache to 6MB, according to the conference agenda. Larger amounts of on-die cache allows frequently repeated instructions to be stored in memory extremely close to the main processors, reducing the time the chip needs to process those instructions.
Intel will pack 410 million transistors onto a die with an area of 374 millimetres squared. The new chip will dissipate 130 watts, the same as the Itanium 2 processor.
The new Itanium also features Intel’s EPIC (explicitly parallel instruction computing) architecture, which requires users to recompile their RISC (reduced instruction set computing) or x86 applications to run on the Itanium processor. The new architecture has made IT managers wary about converting their systems to servers from Hewlett-Packard Co. and Unisys Corp., among others, with the Itanium processor.