At a closely watched chip conference that kicks off in San Francisco Monday, Intel Corp. will highlight some emerging obstacles that need to be overcome if semiconductor performance is to keep up its giddying rate of advance.
For 30 years or more, improvements in manufacturing have dramatically increased the number of transistors that can be packed onto the surface of a chip, which in turn helps boost performance. Intel’s newest chip, the Pentium 4, crams an impressive 42 million transistors on its surface, and that number is likely to be dwarfed in the years ahead.
But as the transistor count increases, so too does the amount of power consumed and heat generated in a processor core. Engineers need to come up with some creative ways to control those variables or the industry could run into some serious problems before the decade is out.
“To date we’ve been limited only by the ability to manufacture cost effectively. Looking forward, we think power and power density become a fundamental limitation that we have to fully address in our technology bag of tricks,” said Pat Gelsinger, an Intel vice president and chief technology officer of the Intel Architecture Group, in a telephone briefing with journalists last week.
Gelsinger will outline the problem Monday morning at the International Solid-State Circuits Conference, a highly technical event where engineers gather to exchange ideas and discuss products under development. His remarks reflect the direction of some of Intel’s own research, but should also be viewed as a call to action for the semiconductor industry as a whole, he said.
Gordon Moore, one of Intel’s cofounders, famously observed in the 1960s that the number of transistors that can be packed onto a chip doubles about every two years. If Intel stays on that trajectory, known as Moore’s Law, then the number of transistors on its chips should pass 200 million by 2005, and reach “well in excess of one billion” by the end of the decade, Gelsinger said.
Using the current methods of semiconductor design, however, “by 2010 we’ll have thermal densities that are greater than a nuclear reactor, and this might be a little bit of a problem,” he said.
The problems won’t come as a surprise to many at the conference, which attracts some of the brightest engineers in the world. Intel and its rivals already are experimenting with new ways of making “cooler” chips. But as computing moves rapidly to small devices like phones and PDAs, the need to address problems of power and heat are becoming more urgent.
Overcoming the challenges should reap great rewards. Processor performance today can be measured in MIPS, or millions of instructions per second. By 2010 performance will be measured in trillions of instructions per second – as fast as today’s powerful supercomputers, which use hundreds of processors working in parallel. The clock frequency of future processors could reach as high as 30GHz, compared with about 1GHz today, Gelsinger said.
But the manufacturing improvements that have boosted chip performance in the past won’t do enough to help with the problems of power and heat on the horizon.
“We just have to get much more aggressive,” Gelsinger said. “To date all that we’ve done is focus on performance. Now we have to focus on MIPS per watt, or how do we get transistors operating fast but doing so very power-efficiently.”
Gelsinger will urge the industry to experiment with new cooling technologies, including the use of new types of liquids that surround a processor core. Another option is to use “heat pipes,” which draw heat from the heart of a processor and disperse it over a wider area. Intel uses heat pipes in some of its mobile processors today.
Another challenge is to make better use of the transistors available. Memory tends to make more efficient use of transistors than logic chips, such as microprocessors, and engineers could experiment with larger cache sizes, or by adding new types of memory that are traditionally handled by separate chips. Another option is to put multiple processors on a single silicon core, which can also be more efficient, Gelsinger said.
Yet another issue is what to do with all the additional transistors available. One idea is to create “special-purpose MIPS,” or dedicating an area of the microprocessor to handle specific, compute-intensive tasks. Candidates for the desktop might include interface applications that let people communicate with computers using speech and even facial gestures. In portable gadgets, MIPS could be assigned to wireless communications and antenna functions. Networking processors could also benefit greatly, allowing data to be shuttled around the Internet more quickly, while servers chips could be tuned to handle much larger streams of traffic.
“We’re on track, and we think Moore’s Law will take us to well in excess of a billion transistors by 2010,” Gelsinger said. “However, to do so and to stay on that track and not be delivering nuclear reactors, we’re going to have to address this limitation of power and power efficiency in a much more aggressive way.”
More information about the IEEE International Solid-State Circuits Conference, in San Francisco through Wednesday, is on the Web at http://www.isscc.org/isscc/.
